Scaling techniques for increasing the density of semiconductor devices may include multi-gate transistors, which are obtained by forming a fin or nanowire-shaped multi-channel active pattern (or silicon body) on a substrate and forming gates on the surface of the multi-channel active pattern. Since multi-gate transistors use three-dimensional (3D) channels, they are easily scaled. However, multi-gate transistors may suffer a short channel effect (SCE) when the drain voltage affects the electric potential in a channel region.